AVG 9.0 FILE SERVER - REV 90.1 Especificaciones Pagina 31

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Getting Started Manual
922157-00 Rev A
23
Back of 9xxSZi-A Slave Acquisition Module
Number and Description
1. ChannelSync PCIe 1
Lane Control Input
2. PCIe 4 Lane Data
Output
3. ChannelSync SMA 10
GHz Clock Input
4. AUX IN rated for 50 Ω
input
5. AC Power Plug
PLEASE NOTE THE FOLLOWING:
Only the back of the 9CZi-A Master Control Module or the back of the
9xxMZi-A Master Acquisition Module has 10 MHz Reference Clock
Input/Output connections.
10 MHz Reference Clock Inputs are specifically intended for
synchronization with other instruments; not between Master and Slave
modules.
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